Sapphire Rapids

In the news cycle today, Intel is announcing an update to its planned deployment of its next generation Xeon Scalable platform known as Sapphire Rapids. Sapphire Rapids is the main platform behind the upcoming Aurora supercomputer, and set to feature support for leading edge technologies such as DDR5, PCIe 5.0, CXL, and Advanced Matrix Extensions. The announcement today is Intel reaffirming its commitment to bringing Sapphire Rapids to market for wide availability in the first half of 2022, meanwhile early customers are currently operating with early silicon for testing and optimization.

Intel to Launch Next-Gen Sapphire Rapids Xeon with High Bandwidth Memory

As part of today’s International Supercomputing 2021 (ISC) announcements, Intel is showcasing that it will be launching a version of its upcoming Sapphire Rapids (SPR) Xeon Scalable processor with...

153 by Dr. Ian Cutress on 6/28/2021

Hot Chips 33 (2021) Schedule Announced: Alder Lake, IBM Z, Sapphire Rapids, Ponte Vecchio

Once a year the promise of super hot potatoes graces the semiconductor world. Hot Chips in 2021 is set to be held virtually for the second successive year, and...

33 by Dr. Ian Cutress on 5/18/2021

Microchip Announces First PCIe 5.0 Switches

Building on their recent announcement of PCIe 5.0 retimers, Microchip has announced their first PCIe 5.0 switches, as part of their Switchtec PFX product line. On paper these look...

40 by Billy Tallis on 2/3/2021

What Products Use Intel 10nm? SuperFin and 10++ Demystified

For our audience that regularly keeps track of Intel’s product portfolio, it would be hard to miss that the naming strategy of Intel’s process node technologies is a bit...

143 by Dr. Ian Cutress on 9/25/2020

Intel Roadmap Update: Alder Lake In H2’21, Ice Lake-SP Late This Year

Among several different updates tucked into Intel’s Q2’2020 earnings report, the company included a brief update on some of their future products. While the bulk of the company’s focus...

64 by Ryan Smith on 7/23/2020

Intel Updates ISA Manual: New Instructions for Alder Lake, also BF16 for Sapphire Rapids

As with any processor vendor, having a detailed list of what the processor does and how to optimize for it is important. Helping programmers also plan for what’s coming...

34 by Dr. Ian Cutress on 4/1/2020

Cadence DDR5 Update: Launching at 4800 MT/s, Over 12 DDR5 SoCs in Development

JEDEC still has not published the DDR5 specification officially, yet it looks like DRAM makers and SoC designers are preparing for the DDR5 launch at full steam. Cadence, which...

20 by Anton Shilov on 3/27/2020

Analyzing Intel’s Discrete Xe-HPC Graphics Disclosure: Ponte Vecchio, Rambo Cache, and Gelato

It has been a couple of weeks since Intel formally provided some high-level detail on its new discrete graphics strategy. The reason for the announcements and disclosures centered around...

49 by Dr. Ian Cutress on 12/24/2019

Intel’s 2021 Exascale Vision in Aurora: Two Sapphire Rapids CPUs with Six Ponte Vecchio GPUs

For the last few of years, when discussing high performance computing, it has been tough to avoid hearing the word ‘exascale’. Even last month, on 10/18, HPC twitter was...

43 by Dr. Ian Cutress on 11/17/2019

Intel Xeon Update: Ice Lake and Cooper Lake Sampling, Faster Future Updates

Emerging workloads will require considerably higher performance, and in order to solve upcoming challenges Intel has adjusted its product roadmaps quite significantly. One of the key things that Intel...

29 by Anton Shilov on 5/9/2019

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