DDR5

One of the critical deficits Intel has to its competition in its server platform is core count – other companies are enabling more cores by one of two routes: smaller cores, or individual chiplets connected together. At its Architecture Day 2021, Intel has disclosed features about its next-gen Xeon Scalable platform, one of which is the move to a tiled architecture. Intel is set to combine four tiles/chiplets through its fast embedded bridges, leading to better CPU scalability at higher core counts. As part of the disclosure, Intel also expanded on its new Advanced Matrix Extension (AMX) technology, CXL 1.1 support, DDR5, PCIe 5.0, and an Accelerator Interfacing Architecture that may lead to custom Xeon CPUs in the future.

Micron’s DRAM Update: More Capacity, Four More 10nm-Class Nodes, EUV, 64 GB DIMMs

During its earnings conference call with investors and financial analysts earlier this week, Micron expressed confidence in its long-term future and strong demand for its products as new applications...

23 by Anton Shilov on 6/28/2019

Intel Agilex: 10nm FPGAs with PCIe 5.0, DDR5, and CXL

Ever since Intel purchased Altera for an enormous amount of money a few years ago (ed: $16.7B), the FPGA portfolio that has been coming out has largely been a...

12 by Ian Cutress on 4/2/2019

SK Hynix Details DDR5-6400

SK Hynix this week revealed some additional technical details about its upcoming DDR5-6400 memory chip at the International Solid State Circuits Conference. The die size of the company’s 16...

10 by Anton Shilov on 2/26/2019

Keysight Reveals DDR5 Testing & Validation System

Keysight, an electronic measurement company, has introduced the industry’s first off-the-shelf testing and validation system for DDR5 DRAM. The N6475A DDR5 Tx compliance test software is aimed at developers...

23 by Anton Shilov on 2/6/2019

SK Hynix Develops First 16 Gb DDR5-5200 Memory Chip, Demos DDR5 RDIMM

SK Hynix on Thursday announced that it had completed development of its first DDR5 memory chip. The new chip offers a capacity of 16 Gb and is said to...

29 by Anton Shilov on 11/15/2018

U.S. Government Indicts Chinese DRAM Maker JHICC on Industrial Espionage; Bans Exports To Firm

The U.S. Department of Commerce this week banned U.S. exports to a China-based maker of DRAM. The DoC believes that Fujian Jinhua Integrated Circuit Company (also known as Fujian...

58 by Anton Shilov on 11/1/2018

Cadence & Micron DDR5 Update: 16 Gb Chips on Track for 2019

Earlier this year Cadence and Micron performed the industry’s first public demonstration of next-generation DDR5 memory. At a TSMC event earlier this month the two companies provided some updates...

18 by Anton Shilov on 10/17/2018

Cadence and Micron Demo DDR5-4400 IMC and Memory, Due in 2019

Cadence this week introduced the industry’s first IP interface in silicon for the current provisional DDR5 specification developed by JEDEC. Cadence’s IP and test chip us fabricated using TSMC’s...

31 by Anton Shilov on 5/3/2018

Samsung Starts Production of 8 Gb DDR4-3600 ICs Using 2nd Gen 10nm-Class Tech

Samsung late on Wednesday said that it had initiated mass production of DDR4 memory chips using its second generation '10 nm-class' fabrication process. The new manufacturing technology shrinks die...

24 by Anton Shilov on 12/20/2017

JEDEC: DDR5 to Double Bandwidth Over DDR4, NVDIMM-P Specification Due Next Year

JEDEC made two important announcements about the future of DRAM and non-volatile DIMMs for servers last week. Development of both is proceeding as planned and JEDEC intends to preview...

38 by Anton Shilov on 4/3/2017

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