As part of the second leg of TSMC's spring technology symposium series, the company offered an update on the state of its 3nm-class processes, both current and future. Building on the back of their current-generation N3E process, the optical shrink of this process technology, N3P, is now on track to enter mass production in the second half of 2024. Thanks to that shrink, N3P is expected to offer both increased performance efficiency as well as increased transistor density over N3E.

N3E in Production, Yielding Well

With N3E already in volume production, TSMC is reporting that they're seeing "great" yields on the second-generation 3nm-class process note. According to the company, the D0 defect density of N3E is at relative parity with N5, matching the defect rate of the older node for the same point in its respective lifecycle. This is no small feat, given the additional complexities that come with developing one last, ever-finer generation of FinFET technology. So for TSMC's bleeding-edge customers such as Apple, who just launched their M4 SoC, this is allowing them to reap the benefits of the improved process node relatively quickly.

"N3E started volume production in the fourth quarter of last year, as planned," a TSMC executive said at the event. "We have seen great yield performance on customers' products, so they did go to market as planned."

TSMC's N3E node is a relaxed version of N3B, eliminating some EUV layers and completely avoiding the usage of EUV double patterning. This makes it a bit cheaper to produce, and in some cases it widens the process window and yields, though it comes at the cost of some transistor density.

N3P on Track For Second-Half 2024

Meanwhile, looking towards the immediate future at TSMC, N3P has finished qualification and its yield performance is close to N3E, according to the company. Being an optical shrink, the N3P node is set to enable processor developers to either increase performance by 4% at the same leakage or reduce power consumption by 9% at the same clocks (previously the range was between 4% ~ 10% depending on design). The new node is also set to boost transistor density by 4% for a 'mixed' chip design, which TSMC defines as a processor consisting of 50% logic, 30% SRAM, and 20% analog circuits.

Advertised PPA Improvements of New Process Technologies
Data announced during conference calls, events, press briefings and press releases
Power -25-30% -32% -5% ~ 10% higher
Performance +10-15% +18% +5% +5%
Fmax @ 1.2V
Chip Density ? ? 1.04x same
SRAM Cell Size 0.0199µm² (-5% vs N5) 0.021µm² (same as N5) ? ?
Late 2022 H2 2023 H2 2024 2025

While it looks like the original N3 (aka N3B) will have a relatively muted lifecycle since Apple has been its only major customer, N3E will be adopted by a wide range of TSMC's customers, which includes many of the industry's biggest chip designers. 

Since N3P is an optical shrink of N3E, it is compatible with its predecessor in terms of IP blocks, process rules, electronic design automation (EDA) tools, and design methodology. As a result, TSMC expects the majority of new tape outs to use N3P, not N3E or N3. This is logical as N3P provides higher performance efficiency than N3E at a lower cost than N3.

The most important aspect of N3P is that it is on track to be production ready in the second half of this year, so expect chip designers to adopt it straight away. 

"We have also successfully delivered N3P technology," the TSMC executive said. "It has passed qualification and yield performance is close to N3E. [The process technology] has also received product customer tape outs and will start on production in the second half of this year. Because of [PPA advantages] of N3P, we expect the majority of tape outs on N3 to go to N3P."

Source: European Technology Symposium 2024



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  • nandnandnand - Monday, May 20, 2024 - link

    Let me put it this way. It's known that SRAM scaling has almost completely halted at around 0.02 µm² (SRAM bitcell size) as of N5/N3, with TSMC even choosing to regress slightly (around 5%) on some of the sub-nodes.

    What I don't know is if there is any difference between N7 and N6, which shrinks logic by 18%. I think the answer is no, so what is the benefit making cache chiplets on N6 instead of N7? Probably nothing. So I'm not sure why Terry is talking about N6 cache chiplets. Both 5800X3D and 7000X3D use N7 for V-Cache.

    N7 is at 0.027 µm², so there would be a scaling benefit from moving to any of the N5/N4/N3 nodes. But the capacity might not be available and it might not be worth the cost.

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