Huge Memory Bandwidth, but not for every Block

One highly intriguing aspect of the M1 Max, maybe less so for the M1 Pro, is the massive memory bandwidth that is available for the SoC.

Apple was keen to market their 400GB/s figure during the launch, but this number is so wild and out there that there’s just a lot of questions left open as to how the chip is able to take advantage of this kind of bandwidth, so it’s one of the first things to investigate.

Starting off with our memory latency tests, the new M1 Max changes system memory behaviour quite significantly compared to what we’ve seen on the M1. On the core and L2 side of things, there haven’t been any changes and we consequently don’t see much alterations in terms of the results – it’s still a 3.2GHz peak core with 128KB of L1D at 3 cycles load-load latencies, and a 12MB L2 cache.

Where things are quite different is when we enter the system cache, instead of 8MB, on the M1 Max it’s now 48MB large, and also a lot more noticeable in the latency graph. While being much larger, it’s also evidently slower than the M1 SLC – the exact figures here depend on access pattern, but even the linear chain access shows that data has to travel a longer distance than the M1 and corresponding A-chips.

DRAM latency, even though on paper is faster for the M1 Max in terms of frequency on bandwidth, goes up this generation. At a 128MB comparable test depth, the new chip is roughly 15ns slower. The larger SLCs, more complex chip fabric, as well as possible worse timings on the part of the new LPDDR5 memory all could add to the regression we’re seeing here. In practical terms, because the SLC is so much bigger this generation, workloads latencies should still be lower for the M1 Max due to the higher cache hit rates, so performance shouldn’t regress.

A lot of people in the HPC audience were extremely intrigued to see a chip with such massive bandwidth – not because they care about GPU or other offload engines of the SoC, but because the possibility of the CPUs being able to have access to such immense bandwidth, something that otherwise is only possible to achieve on larger server-class CPUs that cost a multitude of what the new MacBook Pros are sold at. It was also one of the first things I tested out – to see exactly just how much bandwidth the CPU cores have access to.

Unfortunately, the news here isn’t the best case-scenario that we hoped for, as the M1 Max isn’t able to fully saturate the SoC bandwidth from just the CPU side;

From a single core perspective, meaning from a single software thread, things are quite impressive for the chip, as it’s able to stress the memory fabric to up to 102GB/s. This is extremely impressive and outperforms any other design in the industry by multiple factors, we had already noted that the M1 chip was able to fully saturate its memory bandwidth with a single core and that the bottleneck had been on the DRAM itself. On the M1 Max, it seems that we’re hitting the limit of what a core can do – or more precisely, a limit to what the CPU cluster can do.

The little hump between 12MB and 64MB should be the SLC of 48MB in size, the reduction in BW at the 12MB figure signals that the core is somehow limited in bandwidth when evicting cache lines back to the upper memory system. Our test here consists of reading, modifying, and writing back cache lines, with a 1:1 R/W ratio.

Going from 1 core/threads to 2, what the system is actually doing is spreading the workload across the two performance clusters of the SoC, so both threads are on their own cluster and have full access to the 12MB of L2. The “hump” after 12MB reduces in size, ending earlier now at +24MB, which makes sense as the 48MB SLC is now shared amongst two cores. Bandwidth here increases to 186GB/s.

Adding a third thread there’s a bit of an imbalance across the clusters, DRAM bandwidth goes to 204GB/s, but a fourth thread lands us at 224GB/s and this appears to be the limit on the SoC fabric that the CPUs are able to achieve, as adding additional cores and threads beyond this point does not increase the bandwidth to DRAM at all. It’s only when the E-cores, which are in their own cluster, are added in, when the bandwidth is able to jump up again, to a maximum of 243GB/s.

While 243GB/s is massive, and overshadows any other design in the industry, it’s still quite far from the 409GB/s the chip is capable of. More importantly for the M1 Max, it’s only slightly higher than the 204GB/s limit of the M1 Pro, so from a CPU-only workload perspective, it doesn’t appear to make sense to get the Max if one is focused just on CPU bandwidth.

That begs the question, why does the M1 Max have such massive bandwidth? The GPU naturally comes to mind, however in my testing, I’ve had extreme trouble to find workloads that would stress the GPU sufficiently to take advantage of the available bandwidth. Granted, this is also an issue of lacking workloads, but for actual 3D rendering and benchmarks, I haven’t seen the GPU use more than 90GB/s (measured via system performance counters). While I’m sure there’s some productivity workload out there where the GPU is able to stretch its legs, we haven’t been able to identify them yet.

That leaves everything else which is on the SoC, media engine, NPU, and just workloads that would simply stress all parts of the chip at the same time. The new media engine on the M1 Pro and Max are now able to decode and encode ProRes RAW formats, the above clip is a 5K 12bit sample with a bitrate of 1.59Gbps, and the M1 Max is not only able to play it back in real-time, it’s able to do it at multiple times the speed, with seamless immediate seeking. Doing the same thing on my 5900X machine results in single-digit frames. The SoC DRAM bandwidth while seeking around was at around 40-50GB/s – I imagine that workloads that stress CPU, GPU, media engines all at the same time would be able to take advantage of the full system memory bandwidth, and allow the M1 Max to stretch its legs and differentiate itself more from the M1 Pro and other systems.

M1 Pro & M1 Max: Performance Laptop Chips Power Behaviour: No Real TDP, but Wide Range
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  • darwinosx - Friday, November 5, 2021 - link

    Everything you said is wrong. Reply
  • C@illou - Tuesday, October 26, 2021 - link

    Slight correction, Vulkan works great on windows (and also works on Linux, but that counts the same as "SteamOS"), that makes it the most compatible API. Reply
  • xeridea - Tuesday, October 26, 2021 - link

    Vulkan runs on everything. Reply
  • Qozmo - Tuesday, October 26, 2021 - link

    Worth mentioning that MoltenVK exists officially from Khronos Group which layers Vulcan on top of the MetalAPI enabling Vulcan apps to run on MacOS/iOS Reply
  • Wrs - Monday, October 25, 2021 - link

    Is it just me or does that make no economic sense? When I’m AAA gaming (flashy visuals, complex scenes, high fps) I don’t feel as if I’m looking for light and cool or portable. I’d be on a desk flinging a mouse, or wielding a controller in front of a TV. Reply
  • michael2k - Monday, October 25, 2021 - link

    Maybe it isn't clear, but 'light and cool' means there is lots of headroom for overclocking. From the third page:
    Power Behaviour: No Real TDP, but Wide Range
    Apple doesn’t advertise any TDP for the chips of the devices – it’s our understanding that simply doesn’t exist, and the only limitation to the power draw of the chips and laptops are simply thermals. As long as temperature is kept in check, the silicon will not throttle or not limit itself in terms of power draw.

    You can imagine that in a desktop, with far better cooling and far more available power, that the M1P/M1M might grow well beyond the 92W of observed package power. The Mac Pro with 28 cores and 2 GPUs today will allow the CPU to consume 902W, there is a lot of space for performance to grow!

    So imagine 10x more performance from a desktop Mac with 10 M1P in some kind of fabric (100 cores and 320 GPUs!) or a much smaller number of M1P, maybe 4 (40 cores and 128 GPUs) with each allowed to consume 2.5x as much power
    Reply
  • sean8102 - Tuesday, October 26, 2021 - link

    Problem is developer support. It seems there are only 2 "AAA" macOS AND ARM native games.

    https://www.applegamingwiki.com/wiki/M1_native_com...

    That has to improve A LOT for getting a ARM Mac for gaming to make any sense. Otherwise you're always taking the performance hit of Rosetta 2. Plus not many AAA games are releasing for macOS since they announced the switch to ARM.

    The chips are amazing in terms of performance and efficiency, but getting a mac esp a ARM based one for gaming wouldn't make much sense. At least for now and not unless developer support improves A LOT.
    Reply
  • AshlayW - Tuesday, October 26, 2021 - link

    Clock speeds do not scale with power consumption and Firestorm cores are not designed to reach high clock speeds, these cores would likely not break 3.5 if overclocked (wide, dense design for perf/W). AMD / Intel / NVIDIA's 5nm-class processors will put Apple back in its place for people wanting to NOT be locked into a walled garden from a company adamant on crushing consumer rights. It's just a shame that Apple's silicon engineers are so freakin' good, they're working for the wrong company (and hurting human progress by putting the best wafers/chips in Apple products). Reply
  • valuearb - Tuesday, October 26, 2021 - link

    Lol apple is responsible for more human progress than all the other PC makers combined. Reply
  • MooseNSquirrel - Friday, October 29, 2021 - link

    Only if your metric is marketing based. Reply

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