As part of today’s International Supercomputing 2021 (ISC) announcements, Intel is showcasing that it will be launching a version of its upcoming Sapphire Rapids (SPR) Xeon Scalable processor with high-bandwidth memory (HBM). This version of SPR-HBM will come later in 2022, after the main launch of Sapphire Rapids, and Intel has stated that it will be part of its general availability offering to all, rather than a vendor-specific implementation.

Hitting a Memory Bandwidth Limit

As core counts have increased in the server processor space, the designers of these processors have to ensure that there is enough data for the cores to enable peak performance. This means developing large fast caches per core so enough data is close by at high speed, there are high bandwidth interconnects inside the processor to shuttle data around, and there is enough main memory bandwidth from data stores located off the processor.


Our Ice Lake Xeon Review system with 32 DDR4-3200 Slots

Here at AnandTech, we have been asking processor vendors about this last point, about main memory, for a while. There is only so much bandwidth that can be achieved by continually adding DDR4 (and soon to be DDR5) memory channels. Current eight-channel DDR4-3200 memory designs, for example, have a theoretical maximum of 204.8 gigabytes per second, which pales in comparison to GPUs which quote 1000 gigabytes per second or more. GPUs are able to achieve higher bandwidths because they use GDDR, soldered onto the board, which allows for tighter tolerances at the expense of a modular design. Very few main processors for servers have ever had main memory be integrated at such a level.


Intel Xeon Phi 'KNL' with 8 MCDRAM Pads in 2015

One of the processors that used to be built with integrated memory was Intel’s Xeon Phi, a product discontinued a couple of years ago. The basis of the Xeon Phi design was lots of vector compute, controlled by up to 72 basic cores, but paired with 8-16 GB of on-board ‘MCDRAM’, connected via 4-8 on-board chiplets in the package. This allowed for 400 gigabytes per second of cache or addressable memory, paired with 384 GB of main memory at 102 gigabytes per second. However, since Xeon Phi was discontinued, no main server processor (at least for x86) announced to the public has had this sort of configuration.

New Sapphire Rapids with High-Bandwidth Memory

Until next year, that is. Intel’s new Sapphire Rapids Xeon Scalable with High-Bandwidth Memory (SPR-HBM) will be coming to market. Rather than hide it away for use with one particular hyperscaler, Intel has stated to AnandTech that they are committed to making HBM-enabled Sapphire Rapids available to all enterprise customers and server vendors as well. These versions will come out after the main Sapphire Rapids launch, and entertain some interesting configurations. We understand that this means SPR-HBM will be available in a socketed configuration.

Intel states that SPR-HBM can be used with standard DDR5, offering an additional tier in memory caching. The HBM can be addressed directly or left as an automatic cache we understand, which would be very similar to how Intel's Xeon Phi processors could access their high bandwidth memory.

Alternatively, SPR-HBM can work without any DDR5 at all. This reduces the physical footprint of the processor, allowing for a denser design in compute-dense servers that do not rely much on memory capacity (these customers were already asking for quad-channel design optimizations anyway).

The amount of memory was not disclosed, nor the bandwidth or the technology. At the very least, we expect the equivalent of up to 8-Hi stacks of HBM2e, up to 16GB each, with 1-4 stacks onboard leading to 64 GB of HBM. At a theoretical top speed of 460 GB/s per stack, this would mean 1840 GB/s of bandwidth, although we can imagine something more akin to 1 TB/s for yield and power which would still give a sizeable uplift. Depending on demand, Intel may fill out different versions of the memory into different processor options.

One of the key elements to consider here is that on-package memory will have an associated power cost within the package. So for every watt that the HBM requires inside the package, that is one less watt for computational performance on the CPU cores. That being said, server processors often do not push the boundaries on peak frequencies, instead opting for a more efficient power/frequency point and scaling the cores. However HBM in this regard is a tradeoff - if HBM were to take 10-20W per stack, four stacks would easily eat into the power budget for the processor (and that power budget has to be managed with additional controllers and power delivery, adding complexity and cost).

One thing that was confusing about Intel’s presentation, and I asked about this but my question was ignored during the virtual briefing, is that Intel keeps putting out different package images of Sapphire Rapids. In the briefing deck for this announcement, there was already two variants. The one above (which actually looks like an elongated Xe-HP package that someone put a logo on) and this one (which is more square and has different notches):

There have been some unconfirmed leaks online showcasing SPR in a third different package, making it all confusing.

 

Sapphire Rapids: What We Know

Intel has been teasing Sapphire Rapids for almost two years as the successor to its Ice Lake Xeon Scalable family of processors. Built on 10nm Enhanced SuperFin, SPR will be Intel’s first processors to use DDR5 memory, have PCIe 5 connectivity, and support CXL 1.1 for next-generation connections. Also on memory, Intel has stated that Sapphire Rapids will support Crow Pass, the next generation of Intel Optane memory.

For core technology, Intel (re)confirmed that Sapphire Rapids will be using Golden Cove cores as part of its design. Golden Cove will be central to Intel's Alder Lake consumer processor later this year, however Intel was quick to point out that Sapphire Rapids will offer a ‘server-optimized’ configuration of the core. Intel has done this in the past with both its Skylake Xeon and Ice Lake Xeon processors wherein the server variant often has a different L2/L3 cache structure than the consumer processors, as well as a different interconnect (ring vs mesh, mesh on servers).

Sapphire Rapids will be the core processor at the heart of the Aurora supercomputer at Argonne National Labs, where two SPR processors will be paired with six Intel Ponte Vecchio accelerators, which will also be new to the market. Today's announcement confirms that Aurora will be using the SPR-HBM version of Sapphire Rapids.

As part of this announcement today, Intel also stated that Ponte Vecchio will be widely available, in OAM and 4x dense form factors:

Sapphire Rapids will also be the first Intel processors to support Advanced Matrix Extensions (AMX), which we understand to help accelerate matrix heavy workflows such as machine learning alongside also having BFloat16 support. This will be paired with updates to Intel’s DL Boost software and OneAPI support. As Intel processors are still very popular for machine learning, especially training, Intel wants to capitalize on any future growth in this market with Sapphire Rapids. SPR will also be updated with Intel’s latest hardware based security.

It is highly anticipated that Sapphire Rapids will also be Intel’s first multi compute-die Xeon where the silicon is designed to be integrated (we’re not counting Cascade Lake-AP Hybrids), and there are unconfirmed leaks to suggest this is the case, however nothing that Intel has yet verified.

The Aurora supercomputer is expected to be delivered by the end of 2021, and is anticipated to not only be the first official deployment of Sapphire Rapids, but also SPR-HBM. We expect a full launch of the platform sometime in the first half of 2022, with general availability soon after. The exact launch of SPR-HBM beyond HPC workloads is unknown, however given those time frames, Q4 2022 seems fairly reasonable depending on how aggressive Intel wants to attack the launch in light of any competition from other x86 vendors or Arm vendors. Even with SPR-HBM being offered to everyone, Intel may decide to prioritize key HPC customers over general availability.

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  • Oxford Guy - Sunday, July 11, 2021 - link

    ‘So far, his only answer to consoles seems to be that people should just use mini-ITX PCs, and with little apparent appreciation of what that would mean for the industry or consumers.’

    Once again, speculation rather than factual substance. It’s easy to ‘win’ arguments involving one’s fictional opponents.

    I have said more than that but reading for comprehension rather than dismissal is not your modus operandi.
    Reply
  • mode_13h - Sunday, July 11, 2021 - link

    Well, then paint us your vision of a world without consoles. Reply
  • mode_13h - Sunday, July 11, 2021 - link

    > It’s easy to ‘win’ arguments involving one’s fictional opponents.

    I wouldn't say I'm trying to "win" anything, other than trying to get to the heart of your case and see if it's based on anything that withstands scrutiny.
    Reply
  • Qasar - Sunday, July 11, 2021 - link

    " Once again, speculation rather than factual substance. It’s easy to ‘win’ arguments involving one’s fictional opponents "
    hello pot, meet kettle.
    " I have said more than that but reading for comprehension rather than dismissal is not your modus operandi "
    maybe, but you have posted no proof of this console scam, and just personal opinion. maybe its you that needs to work on their reading comprehension. but considering you also seem to resort to insults and name calling, i wouldnt expect much.
    Reply
  • Oxford Guy - Sunday, July 11, 2021 - link

    Qasar, that you believe posts like that are worthwhile says it all. Reply
  • Qasar - Sunday, July 11, 2021 - link

    just like you are your bs console scam posts, right ? look, either post proof of this bs, admit its just your person opinion, and that you hate consoles.. cause that all it looks like it is.

    again, so far, you have posted NO proof of this bs.
    Reply
  • TheJian - Monday, July 5, 2021 - link

    It's comic how many of you see my AMD posts as negative. I'm trying to get them to make more money by making HIGHER MARGIN chips. How is it negative to tell someone, for the love of GOD, start MAKING NET INCOME, CHARGING MORE etc?

    To bad they don't have a block button on here life wccftech (only good thing about their system).

    I gave tons of data for you to look at. See all those numbers in my post? That is DATA. Learn to debate the data, instead of attacking the messenger.

    https://kubraconsult.files.wordpress.com/2019/07/p...
    https://www.macrotrends.net/stocks/charts/AMD/amd/...
    https://www.macrotrends.net/stocks/charts/AMD/amd/...
    https://www.macrotrends.net/stocks/charts/AMD/amd/...
    Do your own homework, I've given enough data to support my points. You just choose to remain stupid. I'd say ignorant, but, you don't seem to learn no matter how much data is put in front of your face. Compare 2009 to today. Great Q's for 2008, then realization you aren't growing and plummet 2009-2015... I could go on with data all day vs. Intel, NV, etc.

    Feel free to ignore the wall of text and move along. Or grow a pair and try to debate my data.
    Reply
  • mode_13h - Wednesday, July 7, 2021 - link

    > I gave tons of data for you to look at.

    But your premise is flawed. AMD cannot stop the production of console chips. Do you think MS and Sony are stupid? Whatever arrangements they have for wafer supply, you can bet that it's out of AMD's hands.

    Also, the notion that Intel can buy up the 3 nm wafer supply before anyone else, or that it can justify doing so for it shareholders, or that TSMC would even be obligated to sell the wafers in volumes that could damage the prospects for its other customers are all laughable.

    You're living in a fantasy land, not the real world.
    Reply
  • TheJian - Monday, July 5, 2021 - link

    You start with my wall, then write one...LOL. OK.

    You are under the impression you win just because you have the best perf/chip. AMD had that ages ago for same 3-4yrs, and the same thing happened that is happening now, just for different reasons. The first time Intel cheated, bribed, etc, and AMD also had a hard limit of 20% share as that was all their fabs could make. Today, is it much different, AMD has CHOSEN to blow wads of wafers (the best nodes each time) on consoles which is limiting the amount of HIGH MARGIN server/HEDT/GPU sales they could be getting instead. It is that simple.

    You are in fantasy land and don't read enough. Apple is launching 3nm products in sept 2022 and chips are being made/tested now for it. Google TSMC 3nm apple intel and you should get a 100 articles talking about 3nm for 2022 and Intel either in 2022 also or Q1 2023. SAmsung issues have nothing to do with TSMC. Intel has made chips at TSMC for AGES, your are incorrect. They are literally about 8% of TSMC's total output yearly. You really don't read. They rank about 1% behind AMD this year if it all turns out as we've been told. And yes, I think it's as easy as apple writes the largest check, so they get every process first. Intel just has to write one large enough to be 2nd in line and with 18.6B TTM, they certainly have the cash to pay a premium for wafers, and it's legal. You must be too young to remember the last time AMD was here. I was a reseller for AMD then...ROFL.

    HEDT wasn't mentioned by linus, he said niche server and mobile at least, but didn't know about other stuff. Did you read my post or just freak when you saw the wall of data, not text? Jeez, I spend half the post telling AMD how to beat Intel but you just dismissed it all.
    https://hothardware.com/news/apple-intel-racing-de...
    https://www.gizmochina.com/2021/07/02/apple-intel-...
    Intel already testing 3nm designs from TSMC...And goes on to say TSMC 3nm mass production h2 2022. Read more, much of this data has been out for AGES, for example:
    https://www.pcgamer.com/tsmc-confirms-3nm-tech-for...
    Mass production of 3nm h2 2022 again, from Dec 2020. I could probably go back further but you are wasting my time. You are claiming stuff isn't coming that 3 companies 100% involved in this stuff, are ALL claiming next year 3nm devices. You claim all 3 companies, TSMC, Apple, Intel all are lying...OK.

    I don't have to beat you, I just have to stop you from getting wafers, which stops you from getting NET INCOME. I can beat you later or simply bankrupt you and buy you out, as 2.1B units or ARM mobile (PC's in a hand, hooked up to monitor/kb/ms it IS a PC), and apple now making ARM macs, etc. You have an AMD with no defense from FTC now. It will be ARM vs. x86 vs riscv.

    So me some NET INCOME, or STFU.
    https://www.youtube.com/watch?v=NCYNftA4EYM
    LInus 3nm cpus incoming 2022. Take time 50 mins in the wan show and they get to 3nm. They wait the entire vid to talk INtel 3nm 2022. Comments section gives the timestamps of each topic.

    Again, Intel doesn't have to win. I described more than one way to cause damage, and it is easy and legal for them to do. 6nm warhol is already an example of wafers lost to intel ;) That costs you too, if you have to cancel a design, a team's time just got wasted, R&D just wasted, probably some take or pay crap involved, etc. Now imagine Intel does what I said for all of h2 2022 and 2023. This is easy to win for Intel, it would be different if they weren't pulling 21B for 2018-2020 and TTM of 18.6B NET INCOME (not revenue, do you even know the difference?).

    https://www.hardwaretimes.com/intels-5nm-process-n...

    Are you just ignoring news on purpose? Without dropping consoles, I don't see how AMD gets more wafers to assault server or any product line heavily for a few more years. But by that time, everyone is basically on the same field again, but with an AMD who forgot to cash in for 4yrs so far. Share means nothing, if you make no income before I take it back...LOL.
    Reply
  • mode_13h - Wednesday, July 7, 2021 - link

    > AMD has CHOSEN to blow wads of wafers (the best nodes each time) on consoles

    At the time AMD signed up to design the console chips, they had no reason to believe that TSMC couldn't scale capacity to meet all of AMD's demands on top of those console chip orders. Now that the situation has changed, it's too late. AMD doesn't get to decide which wafers are used for console chips.

    > You are in fantasy land and don't read enough.

    Um, maybe you're reading the wrong sort of stuff. Maybe you need to read more about how business actually works.

    > HEDT wasn't mentioned by linus

    You listen too much to Linus Tech Tips. He and WccfTech profit by being sensationalist. They just want views, clicks, and followers.

    > you are wasting my time.

    You're free to leave and stop posting. We won't miss you.

    > 6nm warhol is already an example of wafers lost to intel ;)

    Proof? There are other reasons it could have been canceled.
    Reply

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