Every decade is the decade that tests the limits of Moore’s Law, and this decade is no different. With the arrival of Extreme Ultra Violet (EUV) technology, the intricacies of multipatterning techniques developed on previous technology nodes can now be applied with the finer resolution that EUV provides. That, along with other more technical improvements, can lead to a decrease in transistor size, enabling the future of semiconductors. To that end, Today IBM is announcing it has created the world’s first 2 nanometer node chip.

Names for Nodes

Just to clarify here, while the process node is being called ‘2 nanometer’, nothing about transistor dimensions resembles a traditional expectation of what 2nm might be. In the past, the dimension used to be an equivalent metric for 2D feature size on the chip, such as 90nm, 65nm, and 40nm. However with the advent of 3D transistor design with FinFETs and others, the process node name is now an interpretation of an ‘equivalent 2D transistor’ design.

Some of the features on this chip are likely to be low single digits in actual nanometers, such as transistor fin leakage protection layers, but it’s important to note the disconnect in how process nodes are currently named. Often the argument pivots to transistor density as a more accurate metric, and this is something that IBM is sharing with us.

Transistor Density

Today’s announcement states that IBM’s 2nm development will improve performance by 45% at the same power, or 75% energy at the same performance, compared to modern 7nm processors. IBM is keen to point out that it was the first research institution to demonstrate 7nm in 2015 and 5nm in 2017, the latter of which upgraded from FinFETs to nanosheet technologies that allow for a greater customization of the voltage characteristics of individual transistors.

IBM states that the technology can fit ’50 billion transistors onto a chip the size of a fingernail’. We reached out to IBM to ask for clarification on what the size of a fingernail was, given that internally we were coming up with numbers from 50 square millimeters to 250 square millimeters. IBM’s press relations stated that a fingernail in this context is 150 square millimeters. That puts IBM’s transistor density at 333 million transistors per square millimeter (MTr/mm2).

For comparison:

Peak Quoted Transistor Densities (MTr/mm2)
AnandTech IBM TSMC Intel Samsung
22nm     16.50  
16nm/14nm   28.88 44.67 33.32
10nm   52.51 100.76 51.82
7nm   91.20 237.18* 95.08
5nm   171.30    
3nm   292.21*    
2nm 333.33      
Data from Wikichip, Different Fabs may have different counting methodologies
* Estimated Logic Density

As you can tell, different foundries have different official names with a variety of densities. It’s worth noting that these density numbers are often listed as peak densities, for transistor libraries where die area is the peak concern, rather than frequency scaling – often the fastest parts of a processor are half as dense as these numbers due to power and thermal concerns.


Stacked GAA

With regards the movement to Gate-All-Around / nanosheet transistors, while not explicitly stated by IBM, images show that this new 2nm processor is using a three-stack GAA design. Samsung is introducing GAA at 3nm, while TSMC is waiting until 2nm. Intel by contrast, we believe, will introduce some form of GAA on its 5nm process.

IBM’s 3-stack GAA uses a cell height of 75 nm, a cell width of 40 nm, and the individual nanosheets are 5nm in height, separated from each other by 5 nm. The gate poly pitch is 44nm, and the gate length is 12 nm. IBM says that its design is the first to use bottom dieletric isolation channels, which enables the 12 nm gate length, and that its inner spacers are a second generation dry process design that help enable nanosheet development. This is complimented by the first use of EUV patterning on the FEOL parts of the process, enabling EUV at all stages of the design for critical layers.

Users might be wondering why we’re hearing that IBM is the first to a 2nm chip. IBM is one of the world’s leading research centers on future semiconductor technology, and despite not having a foundry offering of their own, IBM develops IP in collaboration with others for their manufacturing facilities. IBM sold its manufacturing to GlobalFoundries with a 10 year partnership commitment back in 2014, and IBM also currently works with Samsung, and recently announced a partnership with Intel. No doubt the latter two will be partnering with IBM on some level around this new development for its viability in their own production chain.


IBM Albany Research Center

No details on the 2nm test chip have been provided, although at this stage it is likely to be a simplified SRAM test vehicle with a little logic. The 12-inch wafer images showcase a variety of different light diffractions, which likely points to a variety of test cases to affirm the viability of the technology. IBM says that the test design uses a multi-Vt scheme for high-performance and high-efficiency application demonstrations.


Wafer up close

The chip was designed and made at IBM’s Albany research facility, which features a 100,000 sq. ft. clean room. The purpose of this facility is to build on IBM’s expansive patent and licensing portfolio for collaborations with partners.

We have a set of questions with IBM’s experts awaiting response. We also now have an active invitation to go visit, as and when we can travel again.

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  • JoeDuarte - Thursday, May 6, 2021 - link

    This isn't real. They can't produce any actual processors using this 2nm node, nor can anyone else. IBM frequently touts dramatic technological advances like this, but they never materialize as real products humans get to use. I've lost track of all their memory and storage breakthroughs, and Watson turned out to be a dud too. They're the "battery breakthrough" company of the semiconductor world – endless announcements from cloistered labs, never any products.

    All of IBM's partners are the B-team right now, just a list of underperforming companies who haven't had any recent successes. Partnering with Intel will get them exactly nowhere. For reasons I don't understand, Samsung can't keep up with TSMC, and can't even design SoCs that are half as good as Apple's or 90% as good as Qualcomm. It's strange.

    The purported 45% performance boost over 7nm is pretty low given that this is three generations or shrinks later. Two consecutive 20% improvements in performance, two shrinks, gives you a 44% net improvement. So 7nm to 5nm to 3nm should give you that under conservative assumptions. If going from 3nm to 2nm offers no improvement at all, well that's not a win. It's strange that they're claiming a true density improvement over 3nm processes, but performance is actually zero improvement. And that's going with their marketing numbers, so best case... And that's assuming this is a real process node that will exist in our world, which it certainly will not.
    Reply
  • Spunjji - Friday, May 7, 2021 - link

    "They can't produce any actual processors using this 2nm node"
    They don't intend to, either. This is a tech demo to build their patent portfolio that they'll share with partners. The partners may or may not use the tech in their final processes. You'll have no idea either way, so it's not clear how you're so certain that this has never happened before?

    "For reasons I don't understand, Samsung can't keep up with TSMC"
    Semiconductor manufacturing is *really hard*. That's it.
    Reply
  • Alistair - Thursday, May 6, 2021 - link

    Wow a lot of crazy comments in here. Was just reading from Anand's chart that TSMC's 5nm is shipping for almost a year now, and already is almost tied to where Intel is trying to be 3 years from now. Not trying to start a flame war.

    I do find it hilarious someone said "TSMC" has low volume, haha, that's a good joke. Just because it is hard to buy doesn't mean supply is limited, the demand is incredible. Apple is making all their Macs, and iPhones, and iPads, all on 5nm now. That is not low volume. And M1 is not a "small" chip at all.
    Reply
  • Spunjji - Friday, May 7, 2021 - link

    People have opinions, and like to bend facts to match them. Reply
  • aperson2437 - Friday, May 7, 2021 - link

    Globalfoundries should get busy building a 2 nm fab in order to start manufacturing these. I want to see them catch up to TSMC. Easier said than done though I'm sure. Reply
  • Anymoore - Saturday, May 8, 2021 - link

    From the photo, the die size looks pretty big, ~ 800 mm2 maybe? Then the transistor density is ~62.5 MTr/mm2.

    The nanosheets are quite wide, going up to 70 nm. I think these are coarser pitch than Fins, maybe even comparable to 22 nm active area pitch, so the EUV advantage is not clear over here. The usual LELE double patterning would still work.

    The point of nanosheets was not to increase density but to allow gate pitch to shrink, but it seems that did not happen (44 nm).
    Reply
  • Santoval - Sunday, May 9, 2021 - link

    "It’s worth noting that these density numbers are often listed as peak densities, for transistor libraries where die area is the peak concern, rather than frequency scaling – often the fastest parts of a processor are half as dense as these numbers due to power and thermal concerns."

    This bit is very important, since most people are unaware that the listed transistor densities of fabs are just the "peak densities" for non logic parts of dies which provide the highest density and energy efficiency but the lowest performance. For instance Intel has no less than three cell libraries at 10nm, ranging from I believe ~55 million to ~100 million transistors per sq. mm. They only broadly advertise the highest density library, which is barely used, and probably not used at all for S-series desktop parts. I strongly doubt the highest density library of TSMC's 7nm process node is even used for the high performance "big" cores of mobile phone ARM processors. It might or might not be employed on the small cores which are clocked up to 2 GHz tops.

    As for your table with the projected peak transistor densities I thought Intel said they were going to be more conservative with the scaling of their 7nm node and "only" target a x2 density over their 10nm node. That would place the peak density of their 7nm node at ~200 million transistors per mm^2. ~237 million transistors is a scaling of x2.37, not x2. I think wikichip calculated Intel's peak density at 7nm based on their previous x2.35 - x2.40 scaling (from 14nm to 10nm), not on their new more conservative target.
    Reply

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