Investigating Performance of Multi-Threading on Zen 3 and AMD Ryzen 5000by Dr. Ian Cutress on December 3, 2020 10:00 AM EST
- Posted in
- Zen 3
- Ryzen 5000
- Ryzen 9 5950X
For simplicity, we are listing the percentage performance differentials in all of our CPU testing – the number shown is the % performance of having SMT2 enabled compared to having the setting disabled. Our benchmark suite consists of over 120 tests, full details of which can be found in our #CPUOverload article.
Here are the single threaded results.
|Single Threaded Tests
AMD Ryzen 9 5950X
Interestingly enough our single threaded performance was within a single percentage point across the stack (SPEC being +1.2%). Given that ST mode should arguably give more resources to each thread for consistency, the fact that we see no difference means that AMD’s implementation of giving a single thread access to all the resources even in SMT mode is quite good.
The multithreaded tests are a bit more diverse:
AMD Ryzen 9 5950X
|3D Particle Movement||100%||165.7%|
|3DPM with AVX2||100%||177.5%|
|HandBrake 4K HEVC||100%||107.9%|
Here we have a number of different factors affecting the results.
Starting with the two tests that scored statistically worse with SMT2 enabled: yCruncher and AIBench. Both tests are memory-bound and compute-bound in parts, where the memory bandwidth per thread can become a limiting factor in overall run-time. yCruncher is arguably a math synthetic benchmark, and AIBench is still early-beta AI workloads for Windows, so quite far away from real world use cases.
Most of the rest of the benchmarks are between a +5% to +35% gain, which includes a number of our rendering tests, molecular dynamics, video encoding, compression, and cryptography. This is where we can see both threads on each core interleaving inside the buffers and execution units, which is the goal of an SMT design. There are still some bottlenecks in the system affecting both threads getting absolute full access, which could be buffer size, retire rate, op-queue limitations, memory limitations, etc – each benchmark is likely different.
The two outliers are 3DPM/3DPMavx, and Corona. These three are 45%+, with 3DPM going 66%+. Both of these tests are very light on the cache and memory requirements, and use the increased Zen3 execution port distribution to good use. These benchmarks are compute heavy as well, so splitting some of that memory access and compute in the core helps SMT2 designs mix those operations to a greater effect. The fact that 3DPM in AVX2 mode gets a higher benefit might be down to coalescing operations for an AVX2 load/store implementation – there is less waiting to pull data from the caches, and less contention, which adds to some extra performance.
In an ideal world, both threads on a core will have full access to all resources, and not block each other. However, that just means that the second thread looks like it has its own core completely. The reverse SMT method, of using one global core and splitting it into virtual cores with no contention, is known as VISC, and the company behind that was purchased by Intel a few years ago, but nothing has come of it yet. For now, we have SMT, and by design it will accelerate some key workloads when enabled.
In our CPU results, the single threaded benchmarks showed no uplift with SMT enabled/disabled in our real-world or synthetic workloads. This means that even in SMT enabled mode, if one thread is running, it gets everything the core has on offer.
For multi-threaded tests, there is clearly a spectrum of workloads that benefit from SMT.
Those that don’t are either hyper-optimized on a one-thread-per-core basis, or memory latency sensitive.
Most real-world workloads see a small uplift, an average of 22%. Rendering and ray tracing can vary depending on the engine, and how much bandwidth/cache/core resources each thread requires, potentially moving the execution bottleneck somewhere else in the chain. For execution limited tests that don’t probe memory or the cache at all, which to be honest are most likely to be hyper-optimized compute workloads, scored up to +77% in our testing.
Post Your CommentPlease log in or sign up to comment.
View All Comments
dotjaz - Thursday, December 3, 2020 - linkDo you understand what "S(imultaneous)" in SMT means? Barrel processors are by definition NOT simultaneous. They switch between threads.
quadibloc - Friday, December 4, 2020 - linkThat all depends. There could be a unit that switches between threads to dispatch instructions into the pipeline, but instructions from all the threads are simultaneously working on calculations in the pipeline. I'd call that a way to implement SMT.
Elstar - Friday, December 4, 2020 - linkGuys, I've got bad news for you. The difference between a barrel processor ("temporal multithreading") and SMT is all about the backend, not the frontend. I.e. whether the processor is superscalar or not. Otherwise there is no difference. They duplicate hardware resources and switch between them. And the frontend (a.k.a. the decoder) switches temporally between hardware threads. There are NOT multiple frontends/decoders simultaneously feeding one backend pipeline.
Elstar - Friday, December 4, 2020 - linkFor example the "SMT4" Intel Xeon Phi has a design weakness where three running threads per core get decoded as if four threads were running. (And yes, just one or two running threads per core get decoded efficiently.)
dotjaz - Thursday, December 3, 2020 - linkYou nailed 2 letters out of 3, gj.
Luminar - Thursday, December 3, 2020 - linkTalk about being uninformed.
MenhirMike - Thursday, December 3, 2020 - linkWill be interesting to see if this looks different with Quad-Channel Threadripper or Octo-Channel EPYC/TR Pro CPUs, since 16 Cores/32 Threads with 2 channels of memory doesn't seem very compute-friendly. Though it's good to see that "SMT On" is still the reasonable default it's pretty much always has been, except in very specific circumstances.
schujj07 - Thursday, December 3, 2020 - linkAlso would be interesting to see this on a 6c/12t or 8c/16t CPU.
CityBlue - Thursday, December 3, 2020 - linkIn your list of "Systems that do not use SMT" you forgot:
* All x86 from Intel with CPU design vulnerabilities used in security conscious environments
MenhirMike - Thursday, December 3, 2020 - linkTo be fair, "x86" and "security conscious" are already incompatible on anything newer than a Pentium 1/MMX. Spectre affects everything starting with the Pentium Pro, and newer processors have blackboxes in the form of Intel ME or AMD PSP. You can reduce the security risk by turning off some performance features (and get CPUs without Intel ME if you're the US government), but this is still just making an inherently insecure product slightly less insecure.