Arm and TSMC this week unveiled their jointly developed proof-of-concept chip that combines two quad-core Cortex-72-based 7 nm chiplets on TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) interposer. The two chips are connected using the company’s Low-voltage-IN-Package-INterCONnect (LIPINCON) interface. The chip is meant to showcase potential of Arm’s and TSMC’s technologies for high-performance computing applications.

Large SoCs are hard and expensive to manufacture with decent yields using leading-edge process technologies these days. In fact, many elements of these SoCs do not need to be produced using the latest nodes at all. As a result, many chipmakers turn to the so-called chiplet design approach that relies on multiple smaller dies optimized for a particular function and produced using an appropriate process technology. Smaller dies afford better yields and better binning, allowing for a quicker return on investment. These smaller dies need to communicate with each other using a high-bandwidth low-latency and low-power inter-chiplet connections and the latter are the corner stone of any chiplet design.

The proof-of-concept system contains two chiplets made using TSMC’s N7 process technology and placed on a CoWoS interposer. Each chiplet features four Arm Cortex-A72 cores running at a whopping 4 GHz (this core was designed to run at <2 GHz frequencies inside mobile SoCs) that are interconnected using an on-die network-on-chip (NoC) mesh bus operating at 4 GHz. The cores are equipped with a 2 MB L2 cache (512 KB per core) as well as a 6 MB unified L3 cache.

The two chips are connected to each other using a LIPINCON die-to-die inter-chiplet connection that operates at 8 GT/s data transfer rate at 0.3 V and offers 320 GB/s bandwidth. When it comes to overall efficiency of LIPINCON on CoWoS, TSMC says that it features a 0.56 pJ/bit (pico-Joules per bit) power efficiency as well as a 1.6 Tb/s/mm2 (terabits per second per square millimeter) bandwidth density.

The proof-of-concept chiplet system was taped out in December 2018, and made in April 2019, so both Arm and TSMC had plenty of time to play with it. The chip will never be sold in volume, but it proves that technologies by the two companies can enable designers to build complex chiplet-based products with unique characteristics. THe companies are hoping that now this technology is proven that its customers will take advantage of it.

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Source: TSMC

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  • Death666Angel - Saturday, September 28, 2019 - link

    Yeah, the numbers are impressive. But one of those technologies is out already and one is just in the proof of concept stages. :) I'd expect new technology to be better than the old stuff. :D
  • eastcoast_pete - Saturday, September 28, 2019 - link

    I consider an interconnect consuming about 70% less power at about 75% of the speed at least potentially better, depending on the use scenario. IF is very capable and, yes, already out, but many have pointed out that the power use by the interconnect is probably the main reason why AMD's 7 nm chips have just about pulled even with Intel's forever 14 nm on power/performance.
  • AlexDaum - Sunday, September 29, 2019 - link

    I think a lot of the power savings are possible because the use of a silicon interposer compared to a standard substrate for Infinity Fabric.
    To me CoWoS seems more like how HBM memory is connected to GPUs than Infinity Fabric.
  • Robo Jones - Friday, September 27, 2019 - link

    This design makes me think Apple will use their chips in all products. All they need to drop in another A13 chiplet for a MacBook Pro or Mac Pro.
  • Santoval - Friday, September 27, 2019 - link

    Interesting. I guess the TDP was not reported but (due to the much higher clock than the max clock the A72 core was designed for) it must be quite high. Perhaps in the 35W - 45W range?
  • ballsystemlord - Saturday, September 28, 2019 - link

    Your caps lock got stuck on. :)
    "THe companies are hoping that now this technology is proven that its customers will take advantage of it."

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