ARM moves at an aggressive pace, pushing out new processor IP on a yearly cadence. It needs to move fast partly because it has so many partners across so many industries to keep happy and partly because it needs to keep up with the technology its IP comes into contact with, everything from new process nodes to higher quality displays to artificial intelligence. To keep pace, ARM keeps multiple design teams in several different locations all working in parallel.

At its annual TechDay event last year, held at one such facility in Austin, Texas, ARM introduced the Mali-G71 GPU—the first to use its new Bifrost GPU architecture—and the Cortex-A73 CPU—a new big core to replace the A72 in mobile. Notably absent, however, was a new little core.

Another year, another TechDay, and another ARM facility (this time in Cambridge, UK)—can only mean new ARM IP. Over the span of several days, we got an in-depth look at its latest technologies, including DynamIQ, the Mali-G72 GPU, the Cortex-A75, and (yes, finally) the successor to the A53: Cortex-A55.

The A53 was announced alongside the A57 and has been in use for several years, both on its own or as the little core in a big.LITTLE configuration. It’s been hugely successful, with more than 40 licensees and 1.7 billion units shipped in just 3 years. But during this time ARM introduced new big cores on a yearly cadence, moving from A57 to A72 to A73. The A53 remained unchanged, however, even as the performance gap between the big and little cores continued to grow.

Predictably then, the focus for A55 was on improving performance. The A53’s dual-issue, in-order core, which serves as the starting point for A55, already delivers good throughput, so ARM focused on improving the memory system. A new data prefetcher, an integrated L2 cache that reduces latency by 50%, and an extra level of L3 cache (among other changes) give the A55 significantly better memory performance—quantified by a nearly 2x improvement in the LMBench memory copy test. The numbers provided by ARM also show an 18% performance gain in SPECint 2006 and an even bigger 38% gain in SPECfp 2006 relative to the A53. These numbers, as well as the others shown in the chart, comparing the A55 and A53 are at the same frequency, same L1/L2 cache sizes, same compiler, etc. and are meant to be a fair comparison. The actual gains should actually be a little higher, because partner SoCs will benefit from adding the L3 cache, which these numbers do not include.

The additional performance does not come for free, however. Power consumption is up 3% relative to the A53 (iso-process, iso-frequency), but power efficiency still improves by 15% when running SPECint 2000 because of its higher performance.

The A55 includes several new features too that will help it expand into new markets. Virtual Host Extensions (VHE) are very important for the automotive market and the advanced safety and reliability features, including architectural RAS support and ECC/parity for all levels of cache are critical for many applications, including automotive and industrial. There’s new features for infrastructure applications too, including a new Int8 dot product instruction (useful for accelerating neural networks). Because A55 is compatible with DynamIQ, it also gets cache stashing and access to a 256-bit AMBA 5 CHI port.

When ARM announced the A73 last year, it talked a lot about improving sustained performance and working within a tight thermal envelope. In other words, the A73 was all about improving power efficiency. The A75 goes in a different direction: Taking advantage of the A73’s thermal headroom, ARM focused on improving performance while maintaining the same efficiency as the A73.

Our previous performance testing revealed mixed results when comparing the A73 to the A72—not too surprising given the significant differences in microarchitecture—with the A73 generally outpacing the A72 by a small margin for integer tasks but falling behind the older CPU in floating point workloads. Things look better for the A75, at least based on ARM’s numbers, which show noticeable gains over the A73 in both integer and floating-point workloads as well as memory streaming.

The graph above shows that the A75 operating at 3GHz on a 10nm node achieves better performance and the same efficiency as an A73 operating at 2.8GHz on a 10nm node, which means the A75 consumes more power. How much more is difficult to tell based on this one simple graph. We know that the A73 is thermally limited when using 4 cores (albeit less so than the A72), so the A75 definitely will be as well. This is not a common scenario, however. Most mobile workloads only fire up 1-2 cores at a time and usually only in short bursts. ARM obviously felt comfortable enough using the A73’s extra thermal headroom to boost performance without negatively impacting sustained performance.

ARM wants to push the A75 into larger form-factor devices with power budgets beyond mobile’s 750mW/core too by pushing frequency higher. Something like a Chromebook or a 2-in-1 ultraportable come to mind. At 1W/core the A75 delivers 25% higher performance than the A73 and at 2W/core the A75’s advantage bumps up to 30% when running SPECint 2006. If anything, these numbers highlight why it’s not a good idea to push performance with frequency alone, as dynamic power scales exponentially.

ARM targeted the A73 specifically at mobile by focusing on power efficiency and removing some features useful for other applications to simplify the design, including no ECC on the L1 cache and no option for a 256-bit AMBA 5 CHI port. With A75, there’s now a clear upgrade path from A72. For the server and infrastructure markets, A75 supports ECC/parity for all levels of cache and AMBA 5 CHI for connecting to larger CCI, CCN, or CMN fabrics, and for automotive and other safety critical applications there’s architectural RAS support, protection against data poisoning, and improved error management.

On the next few pages, we’ll dive deeper into the technical details and features of ARM’s new IP, including DynamIQ (the next iteration of big.LITTLE), Cortex-A75, and Cortex-A55.

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  • Wilco1 - Tuesday, May 30, 2017 - link

    All of the Helio deca cores use Cortex-A72, just like Snapdragon 65x, and the higher clocks of Helio means it beats the 65x like you'd expect. So I'm not sure what your point is?

    Cortex-A53 in Kirin 950 at its highest frequency is ~50% more efficient than Cortex-A72, with the crossover point at around 2.1GHz. On 10nm with Cortex-A55 it may be closer to 2.5GHz.
  • serendip - Tuesday, May 30, 2017 - link

    Yeah, my mistake, I was thinking of Helios with 8x A53s only. Anyway, perf/watt matters at high clock speeds, so a 50% efficient A53 still can't do as much work as an A72 at the same clock speed. I'd rather keep the efficient cores humming along at low speed and have the big cores come online in short bursts, like for app loading or web page rendering. Note that this might not work for constant gaming though, the big cores constantly being on will overheat the phone and kill battery life.

    No easy solutions then.
  • Wardrive86 - Tuesday, May 30, 2017 - link

    2 GHz a53 has the single thread performance of 2.3 GHz Krait 400/1.85 GHz cortex a15. Octa designs often have well over double the multithread performance of say a Snapdragon 800/801. Not low end..very much midrange
  • serendip - Tuesday, May 30, 2017 - link

    But the A53 or A55 at 2+ GHz is a huge power hog that's still slower than a similarly clocked A72 or A75. The octacore branding is a gimmick when all cores are the same design. Performance doesn't scale equally with increasing frequency and power consumption - at one point, it's better to switch the task to a high performance core rather than keep increasing speed on a low performance core.

    A smart design (like the 650/652 which is a flagship killer) would 4x or 6x A55 at low clock rates for multi threaded stuff and 2x A75 for pure single threaded performance, power consumption be damned.
  • Wardrive86 - Tuesday, May 30, 2017 - link

    Snapdragon 625 @ 2.02 GHz and 626 @ 2.3 GHz are certainly not battery hogs. They are both homogenous and ramp clock speed up on all cores very, very often. Much snappier performance than paper specs would suggest and incredible battery life
  • StrangerGuy - Tuesday, May 30, 2017 - link

    Midrange ARM big cores at actual midrange prices are already quite a rarity in the China phone market, let alone outside of it. Since they perform so close to actual flagships SoCs, most OEMs will either price the devices similarly to their actual flagships (cough Samsung A9 Pro), or not doing them altogether. If you ask me who to blame, it will be the non-Apple custom core designers sucking hard at their jobs.

    Besides an A55 SoC with presumably >1K ST GB4 scores are no slouches either, for a $120 device I'm certainly not complaining.
  • serendip - Friday, June 2, 2017 - link

    Maybe the 650/652 was a flash in the pan and the 660 could be a unicorn chip, one that's announced but never deployed. Interestingly Xiaomi moved to the 625 in the Redmi Note 4 and Mi Max 2, whereas predecessor models used the 650. Maybe OEMs really are afraid of good-enough chips in their midrange devices cannibalizing flagship sales.
  • legume - Tuesday, May 30, 2017 - link

    All of these numbers are crap if the cache configs are not stated. DynamIQ is very different and most of the SPEC gains could be from L2/LLC increases. This is all marketing FUD
  • Wilco1 - Tuesday, May 30, 2017 - link

    Forgot to read the article?

    "These numbers, as well as the others shown in the chart, comparing the A55 and A53 are at the same frequency, same L1/L2 cache sizes, same compiler, etc. and are meant to be a fair comparison. The actual gains should actually be a little higher, because partner SoCs will benefit from adding the L3 cache, which these numbers do not include."
  • legume - Wednesday, May 31, 2017 - link

    iso is not the same as knowing the values

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